The Joint Test Access Group (JTAG) defined an architecture for performing boundary scanning on integrated circuits. The original architecture has been expanded to facilitate on-board scan programming (OSP) of programmable elements (e.g., programmable read only memory (PROM), field programmable gate array (FPGA)) on a circuit board in an apparatus (e.g., server). A JTAG architecture used for OSP has typically included one test bus controller (TBC) and one or more test access port (TAP) chains. If an apparatus (e.g., server) had more than one circuit board to be programmed using OSP, then a TAP chain typically spanned the multiple circuit boards.
As server complexity increased, as daisy chains of circuit boards to be controlled and/or programmed by JTAG based OSP lengthened, and as timing issues associated with the increasing complexity and daisy chain lengths became more difficult, JTAG based OSP became difficult, if even possible at all for some apparatus (e.g., enterprise servers). For example, flight time limits of long traces mandated slower clock speeds for JTAG based OSP operations. Just as clock speeds were being forced to go slower, the number of programmable elements to program using OSP was increasing, as was the size of the programmable elements. Additionally, using a single TBC required serial operation where one programmable element would be completely processed before processing of the next programmable element could be started. Programming a set of programmable devices could take an unacceptable amount of time due to the combination of slow clocks and serial operation.